This invention relates generally to clock distribution in integrated circuits and specifically to a clock distribution scheme using a delay lock loop in a programmable logic circuit.
As the level of integration in semiconductor integrated circuits (ICs) increases, signal delays due to parasitic resistance-capacitance loading become larger. This is especially true of high fan-out global signal lines such as synchronous clocks, clock signals in modern programmable logic devices may drive several thousand registers. This is a considerable load to the clock driver. Clock tree structures can be implemented on-chip to minimize clock skew among registers. However, the base trunk clock driver must be capable of driving this clock tree structure and, as a result, a buffer delay of several nanoseconds is typically incurred.
One approach to clock distribution uses a phase locked loop (PLL). This approach uses a phase-locked loop to synchronize a clock distribution signal to a reference clock signal. Since the phase-locked loop generates an internal clock signal and synchronizes it to the reference clock signal from an external source, the reference clock signal does not drive the clock tree structure.
However, some problems exist with implementing a PLL in a typical integrated circuit since the PLL uses analog devices such as a phase frequency detector (PFD), charge pump and low pass filter. These problems include, among others, poor stability and performance in a noisy environment.
It is desirable to use a circuit which achieves clock distribution while minimizing the number of components,
The present invention is a programmable logic device (PLD) with an on-chip clock synchronization circuit to synchronize a reference clock signal. In one implementation, the clock synchronization circuit is a delay-locked loop (DLL) circuit and in another implementation, a phase-locked loop (PLL) circuit. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit provides a synchronized clock signal that is distributed throughout the programmable logic integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The synchronized clock may be programmably connected to or through such programmable resources as look-up tables, sequential machines, registers, function generators, programmable interconnect, multiplexers, and others.
The clock synchronization circuit improves the overall performance of the PLD or FPGA. In particular, the clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. A specific embodiment of the present invention achieves zero nanoseconds clock skew delay. By minimizing clock skew, the programmable integrated circuit performance is improved because there will be no clock skew in the clocks received by individual programmable logical components of the integrated circuit.
In one embodiment, the present invention is a PLD with a digital DLL including a reference clock input for receiving an external reference signal, a feedback clock signal derived from the reference clock signal, and a digital phase detector connected to the reference clock signal and the feedback clock signal. The digital phase detector determines the phase difference between the reference clock signal and the feedback clock signal and outputs a phase error signal output. The DLL further includes a delay selector which is connected to the phase error signal and the reference clock signal. The delay selector outputs a synchronized clock output which may be used to generate the feedback clock signal.
In another embodiment, the programmable logic device includes an array of logic blocks configurable to perform logical functions. Each logic block has inputs and outputs. The programmable logic device includes an interconnect structure including first conductors in a first direction and second conductors in a second direction. The first conductors are between rows of the array and the second conductors are between columns of the array. The interconnect structure is configurable to connect signals from one logic block in the array to another logic block in the array. The programmable logic device includes clock synchronization circuitry to receive a reference clock signal and a feedback clock signal and to generate a synchronized clock output signal. The programmable logic device includes a multiplexer having a first input connected to the reference clock signal and a second input connected to the synchronized clock output signal. The reference clock signal or synchronized clock output signal is selectably coupled to an input of a logic block through the multiplexer. In an implementation, the clock synchronization circuit is a delay-locked loop circuit. The clock synchronization circuit minimizes skew for n clock signals, where each of the n clock signals is received at one of n logic blocks.
In a further embodiment, a programmable logic device includes a clock synchronization circuit which provides a plurality of synchronized clock output signals, each to a different logic block in the array. The clock synchronization circuit minimizes clock skew of the synchronized clock output signals received at the logic blocks.
Other objects, features, and advantages of the present invention will become apparent upon consideration of the following detailed description and the accompanying drawings, in which like reference designations represent like features throughout the figures.